The development of semiconductor lithography has been exponential since the early 60ies and the produced features are getting smaller every second or third year, at the same time as the circuits get faster and more complex. FIG. 1 shows an industry projection of the development for some years forward. Of course the predictions are less certain the farther into the future we look and nobody knows if the electronics industry will still be using transistors in the year 2020. For the next 10 years the projections are more certain and the main uncertainty relates not to “How small?” but to “Exactly when?”.
The errors in lithography can broadly be classified as placement and size errors, or “registration” and “critical dimension”, (“CD”) in the jargon of the trade. There is a more or less fixed relation between the errors that can be allowed in the pattern and the size of the smallest features in the pattern. A rule of thumb is that on the mask the placement of figures has to be within 5% of the design rule and the size of the features should be within 2.5%. These are surprisingly small numbers, but have been justified by both theory and experiments. FIG. 1 also shows the necessary registration and CD (size) control on the mask for each year, assuming that 4X masks will continue to be used. It is seen that the errors are now 1999 in the low tens of nanometers and will in less than 15 years be ten times smaller. At the same time then chips will be larger which means either larger masks or less reduction. Either way it will be difficult to achieve the needed pattern fidelity.
The invention devises a new general method to reduce errors in the lithography in order to achieve total errors that are consistent with the projected lithography development. An important application is for the reduction of clamping errors, being both an important error source and a good example of errors caused by the interaction of several factors.
Clamping Errors
When a glass plate is held it is deformed by the holding device and by its own weight. Furthermore, it can also be distorted by the built-in stress in surface films deposited on it and by the patterning of said films. Semiconductor masks are typically 152×152×6.25 mm and the patterned area may be 127×127 mm. FIG. 2b shows how the bending of a plate 201 under the force of gravitation causes the upper area of the glass to contract. When the plate is released, e.g. held vertically, it springs back to its natural shape, shown in FIG. 2a, and contraction disappears. If a pattern was written on the plate while it was bent, the pattern will be stretched after relief. FIG. 3 shows a diagram with the resulting maximum error when a plate is supported along two opposite edges, as in FIG. 2. Here, the expected lateral position error is shown as a function of the thickness of the plate and the size, i.e. the distance between the two supported sides. The interesting conclusion from FIG. 3 is that the magnitude of errors that can result from inappropriate support of a glass plate is in order of magnitude larger than what is allowable in a high-end mask. Point A shows a standard semiconductor reticle 152×152×6.25 mm and the maximum deviation is around 400 nm. Point B is the new standardised mask format 225×225×9 mm and, despite the fact that the glass plate is thicker, the deviation is above 1 μm. Point C finally illustrates that for large-area masks the problem is even worse: an 800 mm plate 8 mm gives a possible error of 60 μm. It is also seen from FIG. 3 that increasing the thickness of the glass plate is a weak remedy. It is impossible to,increase the thickness of the 800 mm plate to bring the error down to 0.1 μm. The same is valid for the 225 mm mask in B: even a glass cube with the side 225 mm has deviations larger than 10 nm.
I conclusion FIG. 3 shows the magnitude of the gravitational deformation and it shows how everything becomes more difficult for larger mask sizes.
Other Errors
Clamping deformation gives a placement or registration error. Another large source of placement errors in the finished product is the distorsion in the exposure tool, be it a wafer stepper for semiconductors or a projection aligner for display panels. The maskwriter has stage errors, but these are usually well controlled after calibration to a xy metrology system, such as those made commercially available by Nikon and Leica. The placement can also be affected by processing, both because films deposited on or removed from a workpiece have built-in stress and deform the workpiece, and because some process steps cause a shrinkage or warping of the workpiece, e.g. high temperature annealing steps. An important source of errors is the pellicle used on masks. Fitting the frame to the mask plate causes the mask plate to bend.
Other effects make the size of the pattern features come out differently at different location on a mask or on a chip or display panel. There are several possible mechanisms behind this: uneven focus, non-uniform developer agitation, non-uniform photoresist thickness, uneven chrome properties on the mask and uneven film thickness on a wafer or panel, exposure dose variations in the exposure tools, effects of the time between the exposure and development or between resist coating and exposure and effect from non-perfect pre-exposure and post-exposure baking procedures. Size errors also occur because of the basic imaging properties of mask writer and the exposure station. In particular small features tend to come out too small due to finite resolution and features are affected by the presence of other features in the neighbourhood due to stray exposure. These types of size errors are also intimately coupled to shape errors, such as shortening of line ends and rounding of corners. The exact details of the mask and wafer exposure tools also interact with the pattern and create for example grid snap effects, and spurious pattern features.
Mix and Match
The term used in the mask industry is “registration” which really means misregistration from a reference grid, normally an ideal mathematical grid. In the past registration of the finished product to an ideal mathematical grid has not been necessary. If all layers (approximately 25 in a semiconductor chip and 6 in a TFT) are printed using the same type of exposure station systematic and equal behaviour of the exposure stations will cancel, since every layer is distorted in the same way.
However, when resolution is pushed in order to achieve circuit speed and packing density the cost of lithography is rising rapidly, both because of higher tool cost and because of more expensive masks. To make production economical the display and chip manufacturers are trying not to use more sophisticated technology than needed for each layer, so called mix-and-match. Different layers can be printed using different types of exposure tools with different error characteristics. Furthermore the masks may be of different type, e.g. phase-shifting masks for one layer and standard binary masks on another layer. The different types of masks may require them to be written on different maskwriters.
The management of errors is made more complicated by the fact that the exposure tools for critical and non-critical layers may not even have the same exposure field. FIG. 4 shows dies formed on a semiconductor wafer using tools with different fields. The critical layers like the transistor layers are printed with a tool that has a field that accommodates only one die, FIG. 4a. Less critical layers, such as the top metal layers, are printed with a different stepper having a larger field and possibly a different mask reduction factor, FIG. 4b. One or both of the layers can be exposed by a step-and-scan tool, and if both use step and scan they may very well have the scan direction at right angle to each other. Furthermore, it is anticipated that in the future a single die will be exposed in two or more scanning strokes using a so called stitching scanner, FIG. 4c. 
In the past the thinking has been that the masks should be as close to perfect, i.e. as close to the ideal mathematical grid, as possible. Then the masks for different layers can be written on different types of mask-writers or even by different mask making companies for best economy and logistics. When all masks are exposed on the same stepper, or on steppers of the same type, the systematic errors in the stepper will largely cancel. This breaks down in the mix-and-match scenario of FIG. 4a-c. The only straightforward way to resolve the complicated overlay properties of layers printed in different ways is to make each layer print an image that is close to the mathematically ideal.
The invention gives a method to predict the printing errors in a specific exposure station and correct it beforehand by predistorting and prebiasing the pattern in the opposite sense. In this application is described a practical method to manage the lithographic errors al the way to the finished product, and also in the presence of non-ideal mask blanks and clamping structures.